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      ESDi

      Chip-level HBM ESD Analysis Platform

      ESD Analysis Layout Extraction Multi-threaded Simulation

      ESDi platform is a comprehensive suite of advanced full-chip ESD (Electrostatic Discharge) network verification tools. The platform offers HBM verification solutions applicable to various stages of the design process, including schematic level and chip level, and has been recognized and affirmed by leading chip design houses and manufacturers in the industry.

      • Accurate simulation of HBM discharge paths, providing accuracy and speed with nonlinear simulation technology and TLP models

      • Facilitating layout extraction, identifies pads and ESD protection devices, and generates reduced-order models for parasitic layout resistances

      • Simulating pad-to-pad HBM strikes, mapping IR-drops and current densities

      • Identifying overstressed internal-circuit devices, incorrect or missing ESD cells, addressing issues like excessive voltages, electromigration, and imbalanced current distribution

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      Highlights

      • Accurate

        Simulation based approach
        for high level accuracy

      • Excellent

        Industry-leading
        ESD-verification tools

      • Systematic

        All HBM-stress conditions
        for ESD sign-off before tape out

      • Efficient

        Highlights marginal devices
        to avoid costly field failures

      • Comprehensive

        Covering metallization and
        internal circuit sneak-path checks

      • Cost-effective

        Low cost set up, useful
        in all stages of the design flow

      Applications

      • HBM ESD analysis
        for AMS chips

      • HBM ESD analysis
        for automotive chips

      • HBM ESD analysis
        for PMICs

      • HBM ESD analysis
        for digital chips

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